3d7205 doc #96007 data delay devices, inc. 1 12/2/96 3 mt. prospect ave. clifton, nj 07013 monolithic 5-tap fixed delay line (series 3d7205) features packages all-silicon, low-power cmos technology ttl/cmos compatible inputs and outputs vapor phase, ir and wave solderable auto- insertable (dip pkg.) low ground bounce noise leading- and trailing-edge accuracy delay range: 8 through 500ns delay tolerance: 5% or 2ns temperature stability: 3% typical (0c-70c) vdd stability: 2% typical (4.75v-5.25v) minimum input pulse width: 20% of total delay 14-pin dip and 16-pin soic available as drop-in replacements for hybrid delay lines functional description the 3d7205 5-tap delay line product family consists of fixed-delay cmos integrated circuits. each package contains a single delay line, tapped and buffered at 5 points spaced uniformly in time. tap-to-tap (incremental) delay values can range from 8.0ns through 100ns. the input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. the 3d7205 is ttl- and cmos- compatible, capable of driving ten 74ls-type loads, and features both rising- and falling-edge accuracy. the all-cmos 3d7205 integrated circuit has been designed as a reliable, economic alternative to hybrid ttl fixed delay lines. it is offered in a standard 8-pin auto- insertable dip and a space saving surface mount 8-pin soic. data delay devices, inc. 3 1 2 3 4 8 7 6 5 in o2 o4 gnd vdd o1 o3 o5 3d7205z soic (150 mil) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 in n/c n/c o2 n/c o4 n/c gnd vdd n/c n/c o1 n/c o3 n/c o5 3d7205s soic (300 mil) 8 7 6 5 1 2 3 4 in o2 o4 gnd vdd o1 o3 o5 3d7205m dip 3d7205h gull-wing (300 mil) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 in n/c n/c o2 n/c o4 gnd vdd n/c o1 n/c o3 n/c o5 3d7205 dip 3d7205g gull-wing 3d7205k unused pins removed (300 mil) pin descriptions in delay line input o1 tap 1 output (20%) o2 tap 2 output (40%) o3 tap 3 output (60%) o4 tap 4 output (80%) o5 tap 5 output (100%) vcc +5 volts gnd ground n/c no connection table 1 : part number specifications part number tolerances input restrictions dip-8 3d7205m 3d7205h soic-8 3d7205z dip-14 3d7205 3d7205g 3d7205k soic-16 3d7205s total delay ( ns) tap-tap delay ( ns) max operating frequency absolute max oper. freq. min operating pulse width absolute min oper. p.w. -8 -8 -8 -8 40.0 2.0 8.0 1.5 9.52 mhz 71.4 mhz 52.5 ns 7.0 ns -10 -10 -10 -10 50.0 2.5 10.0 2.0 6.67 mhz 50.0 mhz 75.0 ns 10.0 ns -15 -15 -15 -15 75.0 3.8 15.0 2.3 4.44 mhz 33.3 mhz 113 ns 15.0 ns -20 -20 -20 -20 100 5.0 20.0 2.5 3.33 mhz 25.0 mhz 150 ns 20.0 ns -25 -25 -25 -25 125 6.3 25.0 2.5 2.66 mhz 20.0 mhz 188 ns 25.0 ns -30 -30 -30 -30 150 7.5 30.0 3.0 2.22 mhz 16.7 mhz 225 ns 30.0 ns -50 -50 -50 -50 250 12.5 50.0 5.0 1.33 mhz 10.0 mhz 375 ns 50.0 ns -75 -75 -75 -75 375 18.8 75.0 7.5 0.89 mhz 6.67 mhz 563 ns 75.0 ns -100 -100 -100 -100 500 25.0 100 10.0 0.67 mhz 5.00 mhz 750 ns 100.0 ns note: any dash number between 8 and 100 not shown is also available. 1996 data delay devices
3d7205 doc #96007 data delay devices, inc. 2 12/2/96 tel: 973-773- 2299 fax: 973-773-9672 http://www.datadelay.com application notes operational description the 3d7205 five-tap delay line architecture is shown in figure 1. the delay line is composed of a number of delay cells connected in series. each delay cell produces at its output a replica of the signal present at its input, shifted in time. the delay cells are matched and share the same compensation signals, which minimizes tap-to-tap delay deviations over temperature and supply voltage variations. input signal characteristics the frequency and/or pulse width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. the reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. therefore a maximum and an absolute maximum operating input frequency and a minimum and an absolute minimum operating pulse width have been specified. operating frequency the absolute maximum operating frequency specification, tabulated in table 1 , determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. the maximum operating frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. to guarantee the table 1 delay accuracy for input frequencies higher than the maximum operating frequency , the 3d7205 must be tested at the user operating frequency. therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. the programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. nevertheless, it is strongly recommended that the engineering staff at data delay devices be consulted. operating pulse width the absolute minimum operating pulse width (high or low) specification, tabulated in table 1 , determines the smallest pulse width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. the minimum operating pulse width (high or low) specification determines the smallest pulse width of the delay line input signal for which the output delay accuracy tabulated in table 1 is guaranteed. to guarantee the table 1 delay accuracy for input pulse width smaller than the minimum operating pulse width , the 3d7205 must be tested at the user operating pulse width. therefore, to facilitate production and device identification, the part number will include a vdd o1 in o2 o3 o4 temp & vdd compensation gnd figure 1: 3d7205 functional diagram 20% 20% 20% 20% 20% o5
3d7205 doc #96007 data delay devices, inc. 3 12/2/96 3 mt. prospect ave. clifton, nj 07013 application notes (cont?d) custom reference designator identifying the intended frequency and duty cycle of operation. the programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. nevertheless, it is strongly recommended that the engineering staff at data delay devices be consulted. power supply and temperature considerations the delay of cmos integrated circuits is strongly dependent on power supply and temperature. the monolithic 3d7205 programmable delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. the thermal coefficient is reduced to 600 ppm/c , which is equivalent to a variation , over the 0c-70c operating range, of 3% from the room-temperature delay settings. the power supply coefficient is reduced, over the 4.75v- 5.25v operating range, to 2% of the delay settings at the nominal 5.0vdc power supply. it is essential that the power supply pin be adequately bypassed and filtered. in addition, the power bus should be of as low an impedance construction as possible. power planes are preferred. device specifications table 2 : absolute maximum ratings parameter symbol min max units notes dc supply voltage v dd -0.3 7.0 v input pin voltage v in -0.3 v dd +0.3 v input pin current i in -1.0 1.0 ma 25c storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 3 : dc electrical characteristics (0c to 70c, 4.75v to 5.25v) parameter symbol min max units notes static supply current* i dd 15 ma high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level input current i ih 1 m a v ih = v dd low level input current i il -250 m a v il = 0v high level output current i oh -4.0 ma v dd = 4.75v v oh = 2.4v low level output current i ol 4.0 ma v dd = 4.75v v ol = 0.4v output rise & fall time t r & t f 2 ns c ld = 5 pf *i dd (dynamic) = 5 * c ld * v dd * f input capacitance = 10 pf typical where: c ld = average capacitance load/tap ( pf) output load capacitance (c ld ) = 25 pf max f = input frequency ( ghz)
3d7205 doc #96007 data delay devices, inc. 4 12/2/96 tel: 973-773- 2299 fax: 973-773-9672 http://www.datadelay.com silicon delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10k w 10% supply voltage ( vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 w max. rise/fall time: 3.0 ns max. ( measured between 0.6v and 2.4v ) pulse width: pw in = 1.25 x total delay period: per in = 2.5 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. 10k w 470 w 5pf device under test digital scope out1 out2 out4 out3 out trig in ref trig figure 2: test setup device under test (dut) digital scope/ time interval counter pulse generator computer system printer in out5 figure 3: timing diagram t plh t phl per in pw in t rise t fall 0.6v 0.6v 1.5v 1.5v 2.4v 2.4v 1.5v 1.5v v ih v il v oh v ol input signal output signal
|
